(a) Field of the Invention
The present invention relates to a dual port memory, and more particularly, to a dual port memory having a large capacity and provided with a random access port and a serial access port.
(b) Description of Related Art
As the capacity of a memory increases, the number of memory cells connected to each bit line or each word line increases, which in turn increases the parasitic capacitances of the bit lines and the word lines. The increase of the parasitic capacitances deteriorates a high speed operation of the memory. To overcome this problem, technology has been developed to reduce the parasitic capacitances of the bit lines and word lines by dividing the array of memory cells into plural arrays so that a high operational speed of the memory can be obtained.
FIG. 1 shows a conventional dual port memory comprising a random access port and a serial port in a block diagram. The dual port memory, which operates in a RAM cycle or in a transfer cycle, includes n memory cell arrays 11-1n, n word line selecting circuits 21-2n, n sense amplifier circuits 31-3n, n data registers 81-8n, n data transfer circuits 71-7n, n shift registers 91-9n, and a single selector circuit 10.
Each of the n memory cell arrays 11-1n (n=4, for example) is provided with plural word lines, plural bit lines intersecting the plural word lines while being insulated therefrom, and plural memory cells provided at intersections between the bit lines and word lines. When one of the word lines is actuated or caused to have a voltage of a selection level, data stored in corresponding memory cells are output to the bit lines, or data on the bit lines are stored in the memory cells.
Each of the word line selecting circuits 21-2n operates to cause one of the word lines of the corresponding memory cell array to have the selection level in accordance with the address signals ADw1-ADwn. Each of the sense amplifier circuits 31-3n includes plural sense amplifiers SA which are provided For the respective bit lines of a corresponding one of the memory cell arrays 11-1n so as to amplify signals on the bit lines.
Each of the data registers 81-8n includes plural registers corresponding to bit lines of a corresponding one of the memory cell arrays 11-1n. The data registers 81-8n operate to read serial bit data from outside in accordance with register control signals and store the data in the registers, and operate to serially output data held in the registers to the outside in accordance with the register control signals.
The data transfer circuits 71-7n operate in accordance with data transfer signals TG1-TGn to effect data transfer between the bit lines of the memory cell arrays 11-1n and respective registers in the data registers 81-8n via the sense amplifier circuits 31-3n. The shift registers 91-9n operate in response to clock signals CK1-CKn to generate the register control signals supplied to the respective data registers 81-8n. The selector circuit 10 selects one of the data registers 81-8n in accordance with the address signals ADm, and effects data transfer between the selected data register and an outside circuit.
Assuming that the whole capacity of a dual port memory is 512 bits.times.1024 words, and is established by a single memory cell array, then 1,024 memory cells are connected to each bit line. This increases the length of each bit line and the parasitic capacitance of each bit line. However, in a dual port memory divided into n memory cell arrays, for example into four arrays, as described above, the number of memory cells connected to each bit line is equal to 1024/n. Thus, in the case of a memory having four divided arrays, the number of memory cells connected each bit line is 1024/4=256. Accordingly, the parasitic capacitance of each bit line is also reduced to one-n'th. Hence, when there are four divided arrays, the parasitic capacitance is one-fourth. This allows the dual port memory to operate at a higher speed.
Moreover, the above-mentioned dual port memory has an advantage in that during the time when data is output From one of the n memory cell arrays to an outside circuit through a serial access port, data transfer between another memory cell array and a corresponding data register can be effected. This makes it possible to carry out data output without waiting for the completion of data transfer, which also attributes to a higher operational speed.
FIG. 2 shows in greater detail a circuit portion of the dual port memory of FIG. 1. The dual port memory comprises the following circuit elements for each of the memory cell arrays 11-1n. Namely, each data transfer circuit 7j comprises transistors Q71, Q72, . . . equal in number to the bit lines, i.e., the number of bits composing each word of data (in the above mentioned-case, the number is 512). Each data register 8j comprises registers DR1, DR2, . . . and transistors Q81, Q82, . . . both equal in number to the bit lines, and each shift register 9j comprises registers R1, R2, . . . equal in number to the bit lines. In the case where each word data is composed of, 512 bits and the number n of the arrays is equal to 4, the total number of transistors is 512.times.4.times.2, while the total number of registers is also 512.times.4.times.2.
Since the conventional dual port memory as described above has a plurality of divided memory cell arrays, both the length of each bit line and the number of memory cells connected to each bit line can be reduced. Furthermore, during the time when data is output From one of the n memory cell arrays to an outside circuit, data transfer between another memory cell array and a corresponding data register can be effected. These features allow the memory to operate at a high speed.
The conventional dual port memory, however, has a drawback that a data transfer circuit, a data register and a shift register are provided for each of the memory cell arrays, which results in an increased number of circuit elements and an enlarged surface size of memory chips.